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T68 K/S/R 1M Family
Low Power 1M (128Kx8)-Bits Static RAM
DESCRIPTION
The T68K1M, T68S1M, and T68R1M device family is a low power and high performance CMOS SRAM organized as 131,072 words by 8 bits. It operates from 2.7V to 3.6V, 2.2V to 2.7V, and 1.65V to 2.2V. Easy memory expansion is provided by an active LOW chip enable 1 (/CE1), active HIGH chp enable 2 (CE2) and active LOW output enable (/OE) and three-state I/O drivers. Four control pins (/CE1, CE2, /OE, and /WE) fully control the operation mode of the T68 K/S/R 1M device family. An active LOW write enable signal (/WE active low) controls the write/read operation of the memory. When /CE1 and /WE inputs go LOW and CE2 input goes HIGH simultaneously, the device is in write mode and data on the 8 data pins (IO1~IO8) is written into the memory location specified by the address on address pins (A0~A16). When /CE1 and /OE inputs go LOW and CE2 and /WE input stay in HIGH state, the device is in read mode and data in the specified memory address is driven onto the 8 data pins. The 8 data pins will be in high -impedance state if both /OE and /WE pins are in HIGH (inactive) state. The T68 K/S/R 1M device family has an automatically power-down feature when the chip is deselected (/CE1 pin HIGH or CE2 pin LOW). The T68 K/S/R 1M device family is available in JEDEC standard 32-pin 450-mil SOP, 32-pin 8mmx20mm plastic TSOP, 32-pin 8mmx13.4mm plastic STSOP, and 36-ball 6mmx8mm BGA package, also for DICE.
FEATURES
--
Operation voltage... ... ... ... ... ... T68K1M... ... ... ... ... ... ... ... ... ... ... ................. 2.7V ~ 3.6V T68S1M... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .. 2.2V ~ 2.7V T68R1M... ... ... ... ... ... ... ... ... ... .................. 1.65V ~ 2.2V
-- Low active power and standby power -- High access times: 70ns/85ns/100ns -- TTL-compatible inputs and outputs
-- Easy memory expansion with /CE1, CE2 and /OE -- -- Low data retention voltage... ... ... ... ... ... ... ... ... ... ..2.0V (for K), 1.5V (for S), 1.0V (for R) Auto power down when deselected
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T68 K/S/R 1M
PRODUCT FAMILY
Part Number
VCC Range
Speed
Operating Temperature
Power Dissipation Operating (ICC2, Max.) Standby (ISB1, Max.)
Package Type
T68K1MGC -7/-8 T68K1MTC -7/-8 T68K1MSC -7/-8 T68K1MBC -7/-8 T68K1MDC -7/-8 T68S1MGC -7/-8 T68S1MTC -7/-8 T68S1MSC -7/-8 T68S1MBC -7/-8 T68S1MDC -7/-8 T68R1MGC -8/-10 T68R1MTC -8/-10 T68R1MSC -8/-10 T68R1MBC -8/-10 T68R1MDC -8/-10 1.65V~2.2V 85ns/ 100ns 15mA 2uA 2.2V~2.7V Commercial (+0 C~+70 C)
o o
SOP-32 TSOP-32 2.7V~3.6V 20mA 3uA STSOP-32 BGA-36 70ns/ 85ns Dice SOP-32 TSOP-32 20mA 3uA STSOP-32 BGA-36 Dice SOP-32 TSOP-32 STSOP-32 BGA-36 Dice
Part Number
VCC Range
Speed
Operating Temperature
Power Dissipation Operating (ICC2, Max.) Standby (ISB1, Max.)
Package Type SOP-32 TSOP-32
T68K1MGE -7/-8 T68K1MTE -7/-8 T68K1MSE -7/-8 T68K1MBE -7/-8 T68K1MDE -7/-8 T68S1MGE -7/-8 T68S1MTE -7/-8 T68S1MSE -7/-8 T68S1MBE -7/-8 T68S1MDE -7/-8 T68R1MGE -8/-10 T68R1MTE -8/-10 T68R1MSE -8/-10 T68R1MBE -8/-10 T68R1MDE -8/-10 1.65V~2.2V 85ns/ 100ns 15mA 2uA 2.2V~2.7V Extended (-25 C~+85 C)
o o
2.7V~3.6V
20mA
3uA
STSOP-32 BGA-36
70ns/ 85ns
Dice SOP-32 TSOP-32 20mA 3uA STSOP-32 BGA-36 Dice SOP-32 TSOP-32 STSOP-32 BGA-36 Dice
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T68 K/S/R 1M
Part Number
VCC Range
Speed
Operating Temperature
Power Dissipation Operating (ICC2, Max.) Standby (ISB1, Max.)
Package Type
T68K1MGI -7/-8 T68K1MTI -7/-8 68K1MSI -7/-8 T68K1MBI -7/-8 T68K1MDI -7/-8 T68S1MGI -7/-8 T68S1MTI -7/-8 T68S1MSI -7/-8 T68S1MBI -7/-8 T68S1MDI -7/-8 T68R1MGI -8/-10 T68R1MTI -8/-10 T68R1MSI -8/-10 T68R1MBI -8/-10 T68R1MDI -8/-10 1.65V~2.2V 85ns/ 100ns 15mA 2uA 2.2V~2.7V Industrial (-40 C~+85 C)
o o
SOP-32 TSOP-32 2.7V~3.6V 20mA 3uA STSOP-32 BGA-36 70ns/ 85ns Dice SOP-32 TSOP-32 20mA 3uA STSOP-32 BGA-36 Dice SOP-32 TSOP-32 STSOP-32 BGA-36 Dice
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T68 K/S/R 1M
PIN CONFIGURATION
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T68 K/S/R 1M
LOGIC BLOCK
(PIN DESCRIPTION)
Pin Name A0 ~ A16 IO1 ~ IO8 /CE1 CE2 /OE /WE VCC VSS Function Address Input Pins Data Input/Output Pins Chip Enable 1 Input Pin Chip Enable 2 Input Pin Output Enable Input Pin Write Enable Input Pin Power Supply Pin Ground Pin
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T68 K/S/R 1M
TRUTH TABLE
Mode Deselected Deselected Write Read Output Disabled /CE1 H X L L L CE2 X
(1)
/WE X X L H H
/OE X X X L H
I/O1~8 High-Z High-Z Input Output High-Z
Power Standby Standby Active Active Active
L H H H
1. 'X' means don't care. Must be in high or low state.
ABSOLUTE MAXINUM RATINGS (1)
Symbol VCC Parameter Power Supply Voltage (to VSS) Rating -0.5 ~ Vcc.max+1V
(2) (3)
Unit V V V V mA W
O
-0.5 ~ Vcc.max+0.3V VIN/VOUT Input / Output Voltage I OUT PD TSTG TSOLDER Output Current into Outputs (LOW) Power Dissipation Storage Temperature Soldering Temperature and Time C-Grade TA Operating Temperature E-Grade I-Grade
O
-0.5 ~ Vcc+0.5V -0.5 ~ Vcc+0.3V 20 1.0 -65 ~ +150
(2) (3)
C
260 C , 10sec (Lead Only) 0 ~ 70 -25 ~ 85 -40 ~ 85
O
C
1. Stresses greater than those listed in the Absolute Maximum Ratings table may cause permanent damage to the device.Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum ratings conditions for extended periods may affect reliability. 2. For K and S family. 3. For R family.
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T68 K/S/R 1M
RECOMMENDED DC OPERATING RANGE
Symbol T68K1M VCC T68S1M T68R1M VSS T68K1M VIH T68S1M T68R1M T68K1M VIL T68S1M T68R1M Input Low Voltage Input High Voltage Ground Supply Voltage Parameter Rating 2.7 ~ 3.6 2.2 ~ 2.7 1.65 ~ 2.2 0 2.2 ~ VCC+0.5 2.0 ~ VCC+0.5 1.4 ~ VCC+0.5 -0.5 ~ 0.6 -0.5 ~ 0.6 -0.5 ~ 0.4 Unit V V V V V V V V V V
CAPACITANCES (1)
Symbol C IN Parameter Input Capacitance Min. Max. 8pF 10pF Condition Unmeasured pins set to 0V
C IO Input/Output Capacit ance 1. The Capacitances listed in the above table are sampled, not 100% tested.
DATA RENTATION CHARACTERISTICS
Symbol Parameter VCC for Data Retention T68K1M T68S1M T68R1M VCC=2.0V and CMOS Standby mode
(1)
Test Condition
Min. 2.0
Typ. -
Max. 3.6 2.7 2.2 2 3 3 1 2 2 1 2 2 -
Unit
VDR
Standby Mode
1.5 1.0 C-Grade E-Grade I-Grade 0 TRC
V
T68K1M
I DR
Data Retention Current
T68S1M
VCC=1.5V and CMOS Standby mode
(1)
C-Grade E-Grade I-Grade
uA
T68R1M
VCC=1.0V and CMOS Standby mode
(1)
C-Grade E-Grade I-Grade
See data retention waveform TRDR Data Retention Recovery Time Note: 1. Standby mode: /CE1Vcc-0.2V or CE2 Vss+0.2V
TSDR
Data Retention Setup Time
ns ns
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T68 K/S/R 1M
DC ELECTRICAL CHARACTERISTICS
Symbol I LI I LO Parameter Input Leakage Current Output Leakage Current Test Condition VIN = VSS to VCC /CE1=VIH CE2=VIL or /OE=VIH or /WE=VIL, VIO =VSS to VCC T68K1M /CE10.2V, CE2VCC-0.2V, VIN0.2V or VINVCC- 0.2V T68S1M Cycle time = 1s, 100%duty, T68R1M I IO =0mA T68K1M /CE1=VIL, CE2=VIH, VIN=VIH or VIN=VIL, T68S1M Cycle time = min, 100% duty, T68R1M I IO =0mA T68K1M IOL = 2.0mA VOL Output Low Voltage T68S1M IOL = 0.5mA T68R1M IOL = 0.2mA T68K1M IOH = -1.0mA VOH Output High Voltage T68S1M IOH = -0.5mA T68R1M IOH = -0.1mA T68K1M I SB TTL Standby Current T68S1M T68R1M I SB1 CMOS Standby Current
o
Min -1 -1 2.2 2.0 1.4 -
Typ 3 3 2
(1) (1) (1) (1) (1) (1)
Max 1 1 6 6 4 20 20 15 0.4 0.4 0.4 0.2 0.2 0.2
Unit A A
I CC1 Average Operating Current I CC2
mA
15 15 10 -
mA
V
V
/CE1=VIH or CE2= VIL, other inputs = VIH or VIL
mA
T68K1M /CE1VCC-0.2V or T68S1M CE2VSS+0.2V , T68R1M other inputs = 0 to VCC
1.0
(1) (1) (1)
3 3 2 A
1.0 0.8
Note: 1. Ta=25 C, VCC=3.0V (K), VCC=2.5V (S), and VC C=1.8V (R), not 100% tested.
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T68 K/S/R 1M
AC ELECTRICAL CHARACTERISTICS TEST CONDITIONS
Input Pulse Level: 0.2Vcc(OViL), 0.8Vcc(UVIH) Input Rising and Falling Time: 5ns Input and Output Reference Voltage: 0.9V(R), 1.1V(S), 1.5V (K) Output Load: CL = 30pF + one TTL gate
READ CYCLE
Speed Bin Symbol Parameter List -7 (70ns) Min t RC t AA t CO t OE t LZ t OLZ t HZ t OHZ t OH Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold From Address 70 10 5 0 0 10 Max 70 70 35 25 25 10 -8(85ns) Min 85 10 5 0 Max 85 85 40 25 25 15 -10(100ns) Min 100 10 5 0 Max 100 100 50 30 30 ns ns ns ns ns ns ns ns ns Units
WRITE CYCLE
Speed Bin Symbol Parameter List -7 (70ns) Min t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 70 60 0 60 55 0 0 30 0 5 Max 25 -8(85ns) Min 85 70 0 70 60 0 0 35 0 5 Max 25 -10 (100ns) Min 100 80 0 80 70 0 0 40 0 5 Max 30 ns ns ns ns ns ns ns ns ns ns Units
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T68 K/S/R 1M
TIMING DIAGRAMS TIMEING WAVEFORM OF READ CYCLE (1) (Address Controlled, /CE1=/OE=VIL, CE2=/WE=VIH)
TIMEING WAVEFORM OF READ CYCLE (2) (/WE=VIH)
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T68 K/S/R 1M
TIMING WAVEFORM OF WRITE CYCLE (1) (/WE Controlled)
TIMING WAVEFORM OF WRITE CYCLE (2) (/CE1 OR CE2 Controlled)
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T68 K/S/R 1M
DATA RETENTION WAVEFORM (1) (/CE1 Controlled)
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
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T68 K/S/R 1M
PACKAGE DIMENSION
32L PIN SOP (445 mil)
32L PIN TSOP (8x20)
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T68 K/S/R 1M
32L PIN TSOP (8x13.4)
36 BALL BGA ( 6mm x 8mm)
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